`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   21:43:51 04/02/2011
// Design Name:   multi_test_help
// Module Name:   C:/peter/enee408/project/FIRfilter/multi_op_adder_tb.v
// Project Name:  FIRfilter
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: multi_test_help
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module multi_op_adder_tb;

	// Inputs
	reg [7:0] op_1;
	reg [7:0] op_2;
	reg [7:0] op_3;
	reg [7:0] op_4;
	reg clock;

	// Outputs
	wire [7:0] s_out;

	// Instantiate the Unit Under Test (UUT)
	multi_test_help uut (
		.op_1(op_1), 
		.op_2(op_2), 
		.op_3(op_3), 
		.op_4(op_4), 
		.s_out(s_out), 
		.clock(clock)
	);

	initial begin
	$monitor($time,, "a_in = %d, b_in=%d, c_in=%d, d_in=%d,      s_out=%d"	, op_1,op_2,op_3,op_4, s_out);
		// Initialize Inputs
		op_1 = 0;
		op_2 = 0;
		op_3 = 0;
		op_4 = 0;
		clock = 1;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		op_1 = 1;
		op_2 = 0;
		op_3 = 5;
		op_4 = 0;
		#10;
		
		op_1 = 3;
		op_2 = 5;
		op_3 = 9;
		op_4 = 15;
		#10;
		
		op_1 = 100;
		op_2 = 50;
		op_3 = 50;
		op_4 = 50;
		#10;
		
		op_1 = 8;
		op_2 = 200;
		op_3 = 25;
		op_4 = 20;
		#10;
		
		op_1 = 1;
		op_2 = 1;
		op_3 = 250;
		op_4 = 1;
		#10;
		
		op_1 = 50;
		op_2 = 50;
		op_3 = 3;
		op_4 = 150;
		#10;
		

	end
	
	always begin
		#5 clock <= ~clock;
	end
      
endmodule

